发明名称 Method, system and apparatus for low-power storage of processor context information
摘要 A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core.
申请公布号 US8352770(B2) 申请公布日期 2013.01.08
申请号 US20090567707 申请日期 2009.09.25
申请人 INTEL CORPORATION;FLEMING BRUCE L.;CHOUBAL ASHISH V.;MONDAL SANJOY K.;KUTTANNA BELLIAPPA M. 发明人 FLEMING BRUCE L.;CHOUBAL ASHISH V.;MONDAL SANJOY K.;KUTTANNA BELLIAPPA M.
分类号 G06F1/00 主分类号 G06F1/00
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