发明名称 Emulation of power shutoff behavior for integrated circuits
摘要 A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining an emulation module for the IC by including one or more hardware elements for modeling the power architecture in the emulation module; and using the emulation module to simulate changing power levels in one or more power domains of the IC including a power shutoff in at least one power domain.
申请公布号 US8352235(B1) 申请公布日期 2013.01.08
申请号 US20070966602 申请日期 2007.12.28
申请人 CADENCE DESIGN SYSTEMS, INC.;LIN TSAIR-CHIN;ZHU BING;BELETSKY PLATON 发明人 LIN TSAIR-CHIN;ZHU BING;BELETSKY PLATON
分类号 G06G7/54;G06F9/455;G06F17/50 主分类号 G06G7/54
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