发明名称 |
Semiconductor integrated circuit and control method for clock signal synchronization |
摘要 |
There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
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申请公布号 |
US8350595(B2) |
申请公布日期 |
2013.01.08 |
申请号 |
US201213438050 |
申请日期 |
2012.04.03 |
申请人 |
RENESAS ELECTRONICS CORPORATION;KANNO YUSUKE;SAEN MAKOTO;KOMATSU SHIGENOBU;ONOUCHI MASAFUMI |
发明人 |
KANNO YUSUKE;SAEN MAKOTO;KOMATSU SHIGENOBU;ONOUCHI MASAFUMI |
分类号 |
G01R25/00;H03D13/00 |
主分类号 |
G01R25/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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