发明名称 MEMORY CONTROLLER
摘要 <P>PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor memory, in which the error occurrence rate varies with time, without complicating data management and operation. <P>SOLUTION: An ECC circuit 34 can operate in a plurality of error correction modes which have different correction capabilities for data stored in a memory 4. The ECC circuit 34 calculates a syndrome for information data 55 according to an error correction mode which is set by a control part 30, and adds a fixed-length syndrome 53, which is obtained by adding a dummy bit to the calculated syndrome, to the information data 55. When coded data 50 is read, the ECC circuit 34 executes correction processing of the coded data 50 by using the syndrome 53 that is included in the coded data 50. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013003656(A) 申请公布日期 2013.01.07
申请号 JP20110131246 申请日期 2011.06.13
申请人 MEGA CHIPS CORP 发明人 SUGAWARA TAKAHIKO;FUKUSHITA ERI
分类号 G06F12/16 主分类号 G06F12/16
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