| 摘要 |
<P>PROBLEM TO BE SOLVED: To avoid delay in rising of a word line to activation potential and to cope with reduction of a chip size and high-speed of operation speed. <P>SOLUTION: The semiconductor device includes: memory cell capacity (C); a memory cell transistor (NM) provided between the memory cell capacity (C) and a bit line (BLT); a word line (SWL) connected to a control electrode of the memory cell transistor (NM); and a word driver (SWD) for driving the word line (SWL). The word driver (SWD) drives the word line (SWL) by first power supply voltage and second power supply voltage, respectively, in a first period for activating the word line (SWL) and the subsequent second period. The first power supply voltage has higher electrical potential than the second power supply voltage. <P>COPYRIGHT: (C)2013,JPO&INPIT |
