发明名称 CLOCK GENERATION DEVICE AND ELECTRONIC APPARATUS
摘要 <P>PROBLEM TO BE SOLVED: To provide a clock generation device that implements a reduced area by dispensing with a replica circuit, and generate a low jitter output clock by preventing an increase in jitters, and to provide an electronic apparatus. <P>SOLUTION: The clock generation device includes: a phase difference acquisition section for acquiring a phase difference between a target NCO clock and an actual NCO clock in accordance with the value of an accumulator; a delay synchronization circuit for applying a plurality of delays to an input clock in accordance with a signal in phase with the input clock to generate a plurality of delayed clocks; a selection section for selecting and outputting as a selected clock such a delayed clock as is delayed toward the phase of the target NCO clock from the plurality of delayed clocks in response to phase difference information from the phase difference acquisition section; and a second synchronization circuit for synchronizing the NCO clock with the selected clock selected by the selection section to generate an output clock. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2013005050(A) 申请公布日期 2013.01.07
申请号 JP20110131482 申请日期 2011.06.13
申请人 SONY CORP 发明人 IKEDA YUSUKE;SEKIYA AKIHITO;AKEBONO SACHIO
分类号 H03K5/26;H03L7/06;H03L7/081 主分类号 H03K5/26
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