发明名称
摘要 <p>Enhanced electrostatic discharge (“ESD”) protection for an integrated circuit is described. An embodiment relates generally to a circuit for protection against ESD. The circuit has an input/output node and a driver. The driver has a first transistor and a second transistor. A first source/drain node of the first transistor is coupled to the input/output node. A second source/drain node of the first transistor forms a first interior node capable of accumulating charge when electrically floating. A first current flow control circuit is coupled to a discharge node and the second source/drain node of the first transistor. The first current flow control circuit is electrically oriented in a bias direction for allowing accumulated charge to discharge from the first interior node via the first current flow control circuit to the discharge node.</p>
申请公布号 JP2013500679(A) 申请公布日期 2013.01.07
申请号 JP20120522825 申请日期 2010.04.08
申请人 发明人
分类号 H03K19/003;H01L21/82;H01L21/822;H01L27/04 主分类号 H03K19/003
代理机构 代理人
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