发明名称 |
METHOD AND ARCHITECTURE FOR PRE-BOND PROBING OF TSVs IN 3D STACKED INTEGRATED CIRCUITS |
摘要 |
On-chip test architecture and design-for-testability methods for pre-bond testing of TSVs are provided. In accordance with certain embodiments of the invention, a die level wrapper is provided including gated scan flops connected to one end of each TSV. The gated scan flops include a scan flop structure and a gated output. The gated output is controlled by a signal to cause the output of the gated scan flop to either be in a floated state or take the value stored in the flip-flop portion of the gated scan flop. The gated output of the gated scan flop can be used to enable resistance and capacitance measurements of pre-bonded TSVs.
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申请公布号 |
US2013006557(A1) |
申请公布日期 |
2013.01.03 |
申请号 |
US201113172161 |
申请日期 |
2011.06.29 |
申请人 |
DUKE UNIVERSITY;CHAKRABARTY KRISHNENDU;NOIA BRANDON |
发明人 |
CHAKRABARTY KRISHNENDU;NOIA BRANDON |
分类号 |
G06F19/00;G01R1/067;G01R31/02 |
主分类号 |
G06F19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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