发明名称 |
Multi-Layer Interconnect Structure for Stacked Dies |
摘要 |
A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements.
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申请公布号 |
US2013001799(A1) |
申请公布日期 |
2013.01.03 |
申请号 |
US201213608456 |
申请日期 |
2012.09.10 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.;CHANG HUNG-PIN;CHIU CHIEN-MING;WU TSANG-JIUH;SHUE SHAU-LIN;YU CHEN-HUA |
发明人 |
CHANG HUNG-PIN;CHIU CHIEN-MING;WU TSANG-JIUH;SHUE SHAU-LIN;YU CHEN-HUA |
分类号 |
H01L23/498 |
主分类号 |
H01L23/498 |
代理机构 |
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代理人 |
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