发明名称 DEFECT MITIGATION STRUCTURES FOR SEMICONDUCTOR DEVICES
摘要 <p>A method and a semiconductor device (100) for incorporating defect mitigation structures (102) are provided. The semiconductor device (100) comprises a substrate (101), a defect mitigation structure (102) comprising a combination of layers of doped or undoped group IV alloys and metal or non-metal nitrides disposed over the substrate, and a device active layer (103) disposed over the defect mitigation structure (102). The defect mitigation structure (102) is fabricated by depositing one or more defect mitigation layers comprising a substrate nucleation layer (102a) disposed over the substrate (100), a substrate intermediate layer (102b) disposed over the substrate nucleation layer (102a), a substrate top layer (102c) disposed over the substrate intermediate layer (102b), a device nucleation layer (102d) disposed over the substrate top layer (102c), a device intermediate layer (102e) disposed over the device nucleation layer (102d), and a device top layer (102f) disposed over the device intermediate layer (102e). The substrate intermediate layer (102b) and the device intermediate layer (102e) comprise a distribution in their compositions along a thickness coordinate.</p>
申请公布号 WO2013003688(A1) 申请公布日期 2013.01.03
申请号 WO2012US44852 申请日期 2012.06.29
申请人 PIQUANT RESEARCH LLC;PATEL, ZUBIN, P.;FUNG, TRACY, HELEN;TANG, JINSONG;LO, WAI;RAMAMOORTHY, ARUN 发明人 PATEL, ZUBIN, P.;FUNG, TRACY, HELEN;TANG, JINSONG;LO, WAI;RAMAMOORTHY, ARUN
分类号 H01L21/02 主分类号 H01L21/02
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