| 摘要 |
A capacitance distribution detection circuit (102) includes a multiplexer (104), a driver (105), and a sense amplifier (106), and the multiplexer (104) switches states between a first connection state in which first signal lines (HL1 to HLM) are connected to the driver (105) and second signal lines (VL1 to VLM) are connected to the sense amplifier (106), and a second connection state in which the first signal lines (HL1 to HLM) are connected to the sense amplifier (106) and the second signal lines (VL1 to VLM) are connected to the driver (105). The first connection state (A) (a) drives, on the basis of code sequences (di (= di1, di2,..., diN, where i = 1,..., M)) which include +1 or -1 and each of which has a length N, the first signal lines (HL1 to HLM) in parallel so that voltages +V or -V are applied and (b) outputs, along each of the second signal lines (VL1 to VLM), a linear sum of electric charges stored in capacitors corresponding to that respective one of the second signal lines, and (B) estimates, on the basis of an inner product operation of the linear sum of the electric charges outputted along the second signal lines (VL1 to VLM) and the code sequences di, a capacitance of the capacitors formed along that second signal line, for each of the plurality of second signal lines (VL1 to VLM), and the second connection state (C) (a) drives, on the basis of code sequences (di (= di1, di2,..., diN, where i = 1,..., M)), the second signal lines (VL1 to VLM) in parallel so that voltages +V or -V are applied and (b) outputs, along each of the first signal lines (HL1 to HLM), a linear sum of electric charges stored in the capacitors corresponding to that respective one of the first signal lines, and (D) estimates, on the basis of an inner product operation of the linear sum of the electric charges outputted along the first signal lines (HL1 to HLM) and the code sequences di, a capacitance of the capacitors formed along that first signal line, for each of the plurality of first signal lines (HL1 to HLM). |
