发明名称 CACHE CONTROL DEVICE AND PIPELINE CONTROL METHOD
摘要 <p>The cache control device (14) disclosed in the present application has an input unit (210), a first search unit (220), a reading unit (240), a second search unit (230), and a rewriting unit (250). The input unit (210) inputs, to a pipeline, load requests for reading from a directory and store requests for writing a directory, these requests being received from a processor. When it is determined by the first search unit (220) that a directory for which there is a load request exists in a first cache memory or a second cache memory, the reading unit (240) reads the directory from the cache memory. When it is determined by the second search unit (230) that a directory for which there is a store request exists in the first cache memory, the rewriting unit (250) rewrites the directory in the first cache memory.</p>
申请公布号 WO2013001632(A1) 申请公布日期 2013.01.03
申请号 WO2011JP64980 申请日期 2011.06.29
申请人 FUJITSU LIMITED;HATAIDA, MAKOTO;ISHIZUKA, TAKAHARU;YAMAMOTO, TAKASHI;HOSOKAWA, YUKA 发明人 HATAIDA, MAKOTO;ISHIZUKA, TAKAHARU;YAMAMOTO, TAKASHI;HOSOKAWA, YUKA
分类号 G06F12/08 主分类号 G06F12/08
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