| 摘要 |
Floating point adder circuitry 16, 18, 20 is provided with far-path circuitry 18 and near-path circuitry 20. The far-path circuitry utilises a count of trailing zeros TZ and a difference in the input operand exponents to form respective suffix values which are concatenated with the mantissas of the input addends and serve when summed to generate a carry out taking the place of a conventionally calculated sticky bit. Within the near-path, minimum value circuitry 46 is used to calculate the lower of a leading zeros count of the intermediate mantissa produced in a subtraction and the larger of the input operand exponent values such that a left shift applied to the intermediate mantissa value is not able to produce a invalid floating point result due to applying a left shift to remove leading zeros that is too larger and accordingly corresponds to an exponent which cannot be validly represented.
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