发明名称 AGING DEGRADATION DIAGNOSIS CIRCUIT AND AGING DEGRADATION DIAGNOSIS METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 Provided is an aging degradation diagnosis circuit, including: a first delay circuit including a gate array for allowing aging degradation to progress, the first delay circuit being configured to delay an input signal and output a first output signal; a second delay circuit including a gate array having the same number of stages as the first delay circuit, the second delay circuit being configured to delay an input signal and output a second output signal; and an arbitrary delay unit, which is capable of varying a delay period in the second delay circuit by a predetermined amount. A delay comparison unit outputs comparison information obtained by relatively comparing delays between the first output signal and the second output signal. An adjustment unit uses the comparison information, to thereby readjust the delay period in the second delay circuit.
申请公布号 US2013002274(A1) 申请公布日期 2013.01.03
申请号 US201113634188 申请日期 2011.03.11
申请人 NEC CORPORATION;SANEYOSHI EISUKE;NOSE KOICHI 发明人 SANEYOSHI EISUKE;NOSE KOICHI
分类号 G01R31/26 主分类号 G01R31/26
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