| 摘要 |
There is provided a jitter suppression circuit and a jitter suppression method in which both shortening of a pull-in time and high jitter suppression characteristics is satisfied. In a jitter suppression circuit using a digital phase locked loop, both shortening of a pull-in time and high jitter suppression effect can be satisfied by determining whether the loop is in a synchronous state or not using a phase difference between an input clock and an output clock, and changing characteristics of a loop filter by the determination result.
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