发明名称 |
Internal bypassing of memory array devices |
摘要 |
An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation.
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申请公布号 |
US8345497(B2) |
申请公布日期 |
2013.01.01 |
申请号 |
US20100822058 |
申请日期 |
2010.06.23 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;BUNCE PAUL A.;DAVIS JOHN D.;HENDERSON DIANA M.;VORA JIGAR J. |
发明人 |
BUNCE PAUL A.;DAVIS JOHN D.;HENDERSON DIANA M.;VORA JIGAR J. |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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地址 |
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