发明名称 |
Layered chip package and method of manufacturing same |
摘要 |
A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes: a plurality of common electrodes electrically connected to the plurality of common lines; a plurality of non-contact electrodes that are electrically connected to the layer-dependent lines and are not in contact with the semiconductor chip in the layer portion; and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The layer-dependent lines are greater than the common lines in maximum width.
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申请公布号 |
US8344494(B2) |
申请公布日期 |
2013.01.01 |
申请号 |
US201113084053 |
申请日期 |
2011.04.11 |
申请人 |
HEADWAY TECHNOLOGIES, INC.;SAE MAGNETICS (H.K.) LTD.;SASAKI YOSHITAKA;ITO HIROYUKI;IKEJIMA HIROSHI;IIJIMA ATSUSHI |
发明人 |
SASAKI YOSHITAKA;ITO HIROYUKI;IKEJIMA HIROSHI;IIJIMA ATSUSHI |
分类号 |
H01L21/00;H01L23/02;H01L23/48;H01L23/52;H01L29/40 |
主分类号 |
H01L21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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