发明名称 |
Systems and Methods for Reduced Format Non-Binary Decoding |
摘要 |
Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detecting circuit having: a first vector translation circuit, a second vector translation circuit, and a data detector core circuit. The data detecting circuit is operable to receive an input data set and at least one input vector in a first format. The at least one input vector corresponds to a portion of the input data set. The first vector translation circuit is operable to translate the at least one vector to a second format. The data detector core circuit is operable to apply a data detection algorithm to the input data set and the at least one vector in the second format to yield a detected output. The second vector translation circuit operable to translate a derivative of the detected output to the first format to yield an output vector. |
申请公布号 |
US2012331363(A1) |
申请公布日期 |
2012.12.27 |
申请号 |
US201113167771 |
申请日期 |
2011.06.24 |
申请人 |
LI ZONGWANG;CHANG WU;WANG CHUNG-LI;XU CHANGYOU;YANG SHAOHUA;HAN YANG;LSI CORPORATION |
发明人 |
LI ZONGWANG;CHANG WU;WANG CHUNG-LI;XU CHANGYOU;YANG SHAOHUA;HAN YANG |
分类号 |
G06F11/07 |
主分类号 |
G06F11/07 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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