发明名称 MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS
摘要 A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor.
申请公布号 US2012327701(A1) 申请公布日期 2012.12.27
申请号 US201213529985 申请日期 2012.06.21
申请人 NAZARIAN HAGOP;CROSSBAR, INC. 发明人 NAZARIAN HAGOP
分类号 H01L47/00;G11C11/00 主分类号 H01L47/00
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