| 摘要 |
A probe within a Network-on-Chip (NoC) that can calculate a histogram of transaction data is disclosed. Some such histograms are cycles per number of pending transactions, transactions per latency, and transactions per request delay. The number of pending transactions can be measured by a register that is incremented at the start and decremented at the end of each transaction. Latencies can be measured by timers that are allocated and initialized at the start and read at the end of each transaction. Multiple counters can be used for multiple pending transactions. Multiple banks of counters can be used so that multiple transaction interfaces can complete transactions and perform histogram bin threshold comparisons simultaneously. The thresholds separating histogram bins can be programmable.
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