| 摘要 |
An integrated circuit (IC) for a backplane serializer/deserializer (SerDes) system, comprising a first transmitter configured to send first data at a data rate to a second receiver in a second IC, a first receiver configured to receive second data at the data rate from a second transmitter in the second IC, wherein each of a first link and a second link is to the first transmitter, the first receiver, the second transmitter, and the second receiver, and wherein both the first link and the second link combined are configured to transfer the first data from the first transmitter to the second receiver and transfer the second data from the second transmitter to the first receiver at the data rate. |
