摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a skew among serial data transmitted in a parallel bunch. <P>SOLUTION: A parallel-serial conversion circuit includes a plurality of parallel-serial conversion sections having frequency division circuits for generating a clock signal of a first clock period by dividing the frequency of a clock signal of a second clock period, a parallel input circuit for inputting a multi-bit signal in parallel at the first clock period, and a serial output circuit for serially outputting the multi-bit signal input into the parallel input circuit bit by bit at the second clock period. The frequency division circuit of each of the plurality of parallel-serial conversion sections has a synchronization signal interface for synchronizing the output clock signal with the clock signal output by the frequency division circuit of the other parallel-serial conversion section. <P>COPYRIGHT: (C)2013,JPO&INPIT |