<p>This semiconductor device (1) is provided with a memory controller (14) which outputs a plurality of signals (S1 to S3) which are partitioned into three groups, three switching circuits (17 to 19) which are each provided so as to correspond to the respective three groups, a plurality of buffer circuits (B1 to B3) which are partitioned into three groups, and a plurality of external terminals (TA) which are each provided so as to correspond to the respective pluralities of buffer circuits (B1 to B3). Each switching circuit imparts a plurality of signals of a corresponding group to a plurality of buffer circuits of the corresponding group in parallel in an order which corresponds to a selector control signal (SE).</p>
