发明名称
摘要 The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.
申请公布号 JP5107839(B2) 申请公布日期 2012.12.26
申请号 JP20080231978 申请日期 2008.09.10
申请人 发明人
分类号 H01L25/07;H01L25/18 主分类号 H01L25/07
代理机构 代理人
主权项
地址