发明名称 |
Integrated circuit with staggered signal output |
摘要 |
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
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申请公布号 |
US8339878(B2) |
申请公布日期 |
2012.12.25 |
申请号 |
US201113336851 |
申请日期 |
2011.12.23 |
申请人 |
SHAEFFER IAN P.;STOTT BRET;LAU BENEDICT C.;RAMBUS INC. |
发明人 |
SHAEFFER IAN P.;STOTT BRET;LAU BENEDICT C. |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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