| 摘要 |
This is a method of designing a semiconductor device. The method includes: arranging cells used for an electric circuit and wirings respectively connected to gates of the cells in a coordinate region to create chip layout data including the cells, gates and wirings; checking whether each gate included in the chip layout data is in antenna violation; storing antenna violation information in an error-remaining portion library, the antenna violation information representing an antenna violation gate group, in which gates in the antenna violation are contained, in the gates included in the chip layout data; performing lithography simulation for the chip layout data to create predicted layout data after photoresist exposure; selecting the antenna violation gate group from the gates included in the predicted layout data, with reference to the error-remaining library; calculating a calculated value representing a ratio of an area of an wiring of the wirings with respect to an area of a gate of the antenna violation gate group connected to the wiring, for each gate of the antenna violation group; and adjusting a size of the gate of the antenna violation gate group, when the calculated value of the antenna violation group included in the predicted layout data is in a range between a first and second setting value. |
