| 摘要 |
<p>PURPOSE: A digital phase locked loop system and method are provided to control a phase by selectively controlling an oscillator load during each clock cycle. CONSTITUTION: A reference clock input receives a reference clock signal. A digital controlled oscillator(16) outputs a controllable clock signal. A digital detector(14) applies control signals for setting up an output operation signal frequency to the oscillator according to a detected frequency of the output clock signal of a power generator. A phase of the output signal is selectively controlled by the control signals of the digital detector. An input divider(12) is connected to the reference clock input to divide the reference clock signal with one of a plurality of predetermined division ratios. An output divider(18) is connected an output of the oscillator to divide an oscillator output signal with one of the plurality of predetermined division ratios. [Reference numerals] (12) Frequency demultiplier(÷2R); (14) DPFD; (16) DCO; (18) Frequency demultiplier(÷P); (20) Counter(F)</p> |
