发明名称 Reducing Leakage Power in Integrated Circuit Designs
摘要 A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative slack and replacement values are computed for cell instances in the path. One or more cell instances in the path are then replaced with variants based on the replacement values.
申请公布号 US2012324412(A1) 申请公布日期 2012.12.20
申请号 US201213597227 申请日期 2012.08.28
申请人 TIRUMALA SRIDHAR;SYNOPSYS, INC. 发明人 TIRUMALA SRIDHAR
分类号 G06F17/50 主分类号 G06F17/50
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