| 摘要 |
<p>On the basis of a memory access request inputted from a request storage unit (0) through a CPU core unit, an L2 cache control unit searches cache memory and holds in a request storage unit (1) and a request storage unit (2) memory access requests generated by cache misses. A bank abort generation unit calculates for each bank the number of memory access requests to a main storage device on the basis of the memory access requests stored in the request storage units (1 and 2), and, if the calculated number of memory access requests for any of the banks exceeds a prescribed value, sends an access interruption command by sending a bank abort notification to the L2 cache control unit. On the basis of that command, the L2 cache control unit interrupts the processing of memory access requests held in the request storage unit (2). The main storage control unit issues to the main storage device the memory access request stored in the request storage unit (2).</p> |
