发明名称 SAMPLE HOLD CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a sample hold circuit including a sample hold function and multiplexer function, capable of performing the sample hold function and multiplexer function by only using two-phase signals each having an opposite phase. <P>SOLUTION: Two sample hold circuits 10 and 11 comprise: differential amplifiers A1 and A2 having non-inverting input terminals connected to a reference potential; switches turned on and off in response to a control signal &phiv;1 and sampling capacitors C1 and C3; switches turned on and off in response to the control signal &phiv;1 and hold capacitors C2 and C4; and switches turned on and off in response to a control signal &phiv;2. A multiplexer circuit 12 comprises: a differential amplifier A3 having a non-inverting input terminal connected to the reference potential; switches turned on and off in response to the control signals &phiv;1 and &phiv;2; a hold capacitor C5 connected to between an output terminal and an inverting input terminal of the differential amplifier A3. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012252739(A) 申请公布日期 2012.12.20
申请号 JP20110124126 申请日期 2011.06.02
申请人 PANASONIC CORP 发明人 OGITA SHINICHI
分类号 G11C27/02;H03F3/45;H03F3/68 主分类号 G11C27/02
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