发明名称 Method, Device and System for Clock Dejitter
摘要 The present invention discloses a clock dejitter method comprising: a data sending adapter module inputting data with a system clock and using a sending clock to send data; a clock dejitter module associating the system clock with the sending clock of the data sending adapter module using; and the clock dejitter module tracking variations in the system clock and a data enable signal reflecting data sending state by referring to the system clock, and dynamically generating the sending clock varying with the data sending state. The present invention also discloses a clock dejitter apparatus and a data transmission system. The present invention greatly improves the free scheduling processing ability of services and reduces the bit error rate of data transmission while increasing efficiency of large capacity data switch transmission by dynamically adjusting the sending clock.
申请公布号 US2012320960(A1) 申请公布日期 2012.12.20
申请号 US201013519199 申请日期 2010.06.22
申请人 WEI XIAOYI;ZTE CORPORATION 发明人 WEI XIAOYI
分类号 H04B17/00 主分类号 H04B17/00
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