ALLOCATION OF PRESET CACHE LINES

摘要

An apparatus generally having a cache memory and a circuit is disclosed. The circuit may be configured to (i) parse a single first command received from a processor into a first address and a first value and (ii) allocate a first one of a plurality of lines in the cache memory to a buffer in response to the first command. The first line (a) is generally associated with the first address and (b) may have a plurality of first words. The circuit may be further configured to (iii) preset each of the first words in the first line to the first value.