发明名称 LOW-TEMPERATURE WAFER-LEVEL PACKAGING AND DIRECT ELECTRICAL INTERCONNECTION
摘要 Proposed is a low-temperature wafer-level bonding process based on hybrid bonding of a device substrate (3) with a cap substrate (1), which cap substrate (1) features through silicon vias (2), wherein simultaneous mechanical and electrical bonding of different materials at low temperature is used, without a prior planarization of the heterogeneous substrates before the hybrid bonding process. Therein the hybrid bonding process is based on low-temperature direct bonding (LTDB) and transient liquid phase bonding (TLPB, and during the wafer-level hybrid bonding process, ultra-thin AuSn contact pads (9) are forming local electrical interconnects between metallization layers of the device substrate (3) and the through silicon vias (2) of the cap substrate (1) by transient liquid phase bonding (TLPB). During the wafer-level hybrid bonding process simultaneously, a strong mechanical bond is performed in the low-temperature direct bonding (LTDB) by hydrophilic direct bonding of plasma activated Si and Si02 interfaces between device substrate (3) and cap substrate (2).
申请公布号 WO2012171663(A1) 申请公布日期 2012.12.20
申请号 WO2012EP02554 申请日期 2012.06.15
申请人 ETH ZURICH;KUEHNE, STEPHANE 发明人 KUEHNE, STEPHANE
分类号 B81C1/00 主分类号 B81C1/00
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