发明名称 Wafer Level Chip Scale Package with Reduced Stress on Solder Balls
摘要 A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.
申请公布号 US2012319270(A1) 申请公布日期 2012.12.20
申请号 US201113162394 申请日期 2011.06.16
申请人 CHEN YU-FENG;TSAI YU-LING;PU HAN-PING;KUO HUNG-JUI;HUANG YU YI;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 CHEN YU-FENG;TSAI YU-LING;PU HAN-PING;KUO HUNG-JUI;HUANG YU YI
分类号 H01L23/48 主分类号 H01L23/48
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