发明名称 |
METHOD AND SYSTEM FOR A RUN-TIME RECONFIGURABLE COMPUTER ARCHITECTURE |
摘要 |
<p>A reconfigurable computer architecture is disclosed. The reconfigurable computer architecture has a plurality of logic elements, a plurality of connection switching elements, and a plurality of volatile and/or non-volatile configuration random access memories (RAMs). Each of the configuration RAMs is electrically coupled to at least one of the plurality of logic elements or at least one of the connection switching elements.</p> |
申请公布号 |
EP2534583(A1) |
申请公布日期 |
2012.12.19 |
申请号 |
EP20100834124 |
申请日期 |
2010.12.01 |
申请人 |
QUEEN'S UNIVERSITY AT KINGSTON;TRUSTEES OF PRINCETON UNIVERSITY |
发明人 |
ZHANG, WEI;JHA, NIRAJ K.;SHANG, LI |
分类号 |
G06F15/76;G11C11/401;G11C11/41;G11C13/02;H03K19/094 |
主分类号 |
G06F15/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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