发明名称 |
Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits |
摘要 |
In one embodiment of the invention, a method of analysis of a circuit design with respect to within-die process variation is disclosed to generate a design-specific on chip variation (DS-OCV) de-rating factor. The method includes executing a static timing analysis (STA) in an on-chip variation mode using a process corner library. Collecting timing information of the top N critical timing paths. Executing a statistical static timing analysis (SSTA) on the N critical timing paths using timing models characterized for SSTA with sensitivities of delays to process variables. Compare the two timing results and deriving DS-OCV de-rating factors for the clock/data paths to be used in a STA OCV timing analysis to correctly account for the effects of process variations. A user may select to specify DS-OCV de-rating factors for paths or groups of paths and achieve an accurate timing analysis report in a reduced amount of run-time. |
申请公布号 |
US8336010(B1) |
申请公布日期 |
2012.12.18 |
申请号 |
US20100824191 |
申请日期 |
2010.06.27 |
申请人 |
CHANG HONGLIANG;GEROUSIS VASSILIOS;MOLAKALAPALLI SIREESHA;SHRIVASTAVA SACHIN;CADENCE DESIGN SYSTEMS, INC. |
发明人 |
CHANG HONGLIANG;GEROUSIS VASSILIOS;MOLAKALAPALLI SIREESHA;SHRIVASTAVA SACHIN |
分类号 |
G06F9/455;G06F17/50 |
主分类号 |
G06F9/455 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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