发明名称 Semiconductor memory device with a stacked gate including a charge storage layer and a control gate and method of controlling the same
摘要 A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.
申请公布号 US8335125(B2) 申请公布日期 2012.12.18
申请号 US201113285099 申请日期 2011.10.31
申请人 NAKANO TAKESHI;NAKAMURA HIROSHI;HOSONO KOJI;KABUSHIKI KAISHA TOSHIBA 发明人 NAKANO TAKESHI;NAKAMURA HIROSHI;HOSONO KOJI
分类号 G11C8/00 主分类号 G11C8/00
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