发明名称 |
Method to fabricate self-aligned source and drain in split gate flash |
摘要 |
A new structure is disclosed for source/drain bit lines in arrays of MOSFET devices. Rows of conducting regions are formed by ion implantation through openings adjacent to gate structures and in isolation regions separating columns of active areas of the arrays. The openings are filled with insulating material. |
申请公布号 |
US8334558(B2) |
申请公布日期 |
2012.12.18 |
申请号 |
US20030420594 |
申请日期 |
2003.04.22 |
申请人 |
HSIEH CHIA-TA;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY |
发明人 |
HSIEH CHIA-TA |
分类号 |
H01L29/788;H01L21/8247;H01L27/115 |
主分类号 |
H01L29/788 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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