发明名称 |
CLOCK GENERATION CIRCUIT, DRIVING CIRCUIT FOR DISPLAY DEVICE, AND METHOD OF CONTROLLING CLOCK GENERATION CIRCUIT |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock generation circuit capable of recovering from a state where clock generation is stopped more certainly even at power-on or in a normal operation. <P>SOLUTION: A clock generation circuit 1 has: a clock extraction circuit 10 extracting an extracted clock from an embedded signal obtained by superposing data on a clock; and a stop detection circuit 30 detecting the stop of the extracted clock on the basis of the embedded signal and the extracted clock, and outputting a reset signal for resetting the clock extraction circuit to an initial state. <P>COPYRIGHT: (C)2013,JPO&INPIT |
申请公布号 |
JP2012249072(A) |
申请公布日期 |
2012.12.13 |
申请号 |
JP20110119141 |
申请日期 |
2011.05.27 |
申请人 |
RENESAS ELECTRONICS CORP |
发明人 |
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分类号 |
H04L7/033;H03L7/08;H03L7/081;H03L7/095 |
主分类号 |
H04L7/033 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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