| 摘要 |
A phase locked loop (10) comprising: a tuneable oscillator (12); a mixer-based phase sensitive detector (18) to receive input signals from the tuneable oscillator (12) and a reference signal (20); a cycle slip detector (26) to receive input signals from the tuneable oscillator (12) and the reference signal (20), the cycle slip detector (26) being configured to generate an output signal when two consecutive pulses are present in one of its input signals without an intervening pulse in the other of its input signals; coarse tune signal means (32, 34) to receive the output signal generated by the cycle slip detector; and adding means (24) for adding a signal output by the coarse signal means (32, 34) to a signal output by the phase sensitive detector (18) to control the frequency of the tuneable oscillator (12). |
