发明名称 ARITHMETIC CIRCUIT AND A/D CONVERTER
摘要 <P>PROBLEM TO BE SOLVED: To provide an arithmetic circuit that accurately implements a desired multiplying factor while ensuring a desired bandwidth. <P>SOLUTION: The arithmetic circuit includes: an input terminal for inputting an input signal; a plurality of capacitors; and an amplification circuit provided with an amplifying input terminal and an output terminal and configured to amplify a signal input from the amplifying input terminal and output an output signal from the output terminal. A first switch circuit becomes conductive on the basis of a first control signal to connect the plurality of capacitors in parallel between the input terminal and a first voltage terminal for supplying a first voltage. A second switch circuit becomes conductive on the basis of a second control signal to connect first capacitors included in the plurality of capacitors between the amplifying input terminal and a second voltage terminal for supplying a second voltage so as to form a first current path and to connect second capacitors included in the plurality of capacitors between the amplifying input terminal and the output terminal so as to form a second current path. <P>COPYRIGHT: (C)2013,JPO&INPIT
申请公布号 JP2012249068(A) 申请公布日期 2012.12.13
申请号 JP20110119071 申请日期 2011.05.27
申请人 TOSHIBA CORP 发明人 FURUTA MASANORI;ISHII HIROTOMO
分类号 H03F3/343;H03M1/14 主分类号 H03F3/343
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