| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a multi-core LSI for improving stability of an operation. <P>SOLUTION: This multi-core LSI includes: a plurality of CPUs #0, #1 connected to a first shared bus b1; one or more modules m1-mn connected to a second shared bus b2; a shared bus control part 3 which is connected between the first shared bus b1 and the second shared bus b2, and mediates access to modules of the plurality of CPUs #0, #1; and a system controller 9 which monitors whether or not response signals to access request signals of the CPUs #0, #1 are output from modules at access destinations. The system controller 9 outputs a pseudo response signal to the first shared bus b1 via the shared bus control part 3 to terminate the access of the CPUs under the access when the response signals are not output from the modules at the access destinations until predetermined time passes after the access request signals are output from the shared bus control part 3 to the second shared bus b2. <P>COPYRIGHT: (C)2013,JPO&INPIT |
