发明名称 |
Semiconductor Device and Method of Forming a Power MOSFET With Interconnect Structure Silicide Layer and Low Profile Bump |
摘要 |
A semiconductor device has a substrate with a source region and a drain region formed on the substrate. A silicide layer is disposed over the source region and drain region. A first interconnect layer is formed over the silicide layer and includes a first runner connected to the source region and second runner connected to the drain region. A second interconnect layer is formed over the first interconnect layer and includes a third runner connected to the first runner and a fourth runner connected to the second runner. An under bump metallization (UBM) is formed over and electrically connected to the second interconnect layer. A mask is disposed over the substrate with an opening in the mask aligned over the UBM. A conductive bump material is deposited within the opening in the mask. The mask is removed and the conductive bump material is reflowed to form a bump. |
申请公布号 |
US2012313147(A1) |
申请公布日期 |
2012.12.13 |
申请号 |
US201113156281 |
申请日期 |
2011.06.08 |
申请人 |
ANDERSON SAMUEL J.;OKADA DAVID N.;GREAT WALL SEMICONDUCTOR CORPORATION |
发明人 |
ANDERSON SAMUEL J.;OKADA DAVID N. |
分类号 |
H01L27/118;H01L21/82 |
主分类号 |
H01L27/118 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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