摘要 |
Methods and apparatus for accomplishing dynamic frequency/voltage control between at least two processor cores in a multi-processor device or system include receiving busy, idle and wait, time and/or frequency information from a first processor core and receiving busy, idle, wait, time and/or frequency information from a second processor core. The received busy, idle, wait, time and/or frequency information may be correlated to identify patterns of interdependence. The correlated information may be used to determine dynamic frequency/voltage control settings for the first and second processor cores to provide a performance level that accommodates interdependent processes, threads and processor cores. The correlation of received busy, idle, wait, time and/or frequency information may involve generating a consolidated busy/idle pulse train that can then be used to set the frequency or voltage of each processor core independently. |
申请人 |
QUALCOMM INCORPORATED;THOMSON, STEVEN S.;MONDAL, MRIGANKA;HARIHARAN, NISHANT |
发明人 |
THOMSON, STEVEN S.;MONDAL, MRIGANKA;HARIHARAN, NISHANT |