发明名称 VERIFICATION METHOD, COMPUTER-READABLE RECORDING MEDIUM, AND DESIGN VERIFICATION APPARATUS
摘要 A design verification method is disclosed. A computer searches for a path in accordance with a connection relationship between blocks by referring to a netlist stored in a storage part based on terminal information concerning a verification of a circuit which is formed by the blocks. Then, the computer changes an abstraction level of an operation of an out-of-path block which is a block outside the path and is searched for from the blocks described in the netlist.
申请公布号 US2012317526(A1) 申请公布日期 2012.12.13
申请号 US201213469944 申请日期 2012.05.11
申请人 SATO HIROYUKI;KIKUTA HIDEO;FUJITSU SEMICONDUCTOR LIMITED;FUJITSU LIMITED 发明人 SATO HIROYUKI;KIKUTA HIDEO
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址