APPARATUS AND METHOD FOR PROCESSING PARALLEL COMPUTATION USING SIMD ARCHITECTURE

摘要

PURPOSE: A parallel arithmetic processing device with an SIMD(Single Instruction Multiple Data) processor and a method thereof are provided to reduce a size of the whole hardware logic with the efficient use of memory by performing a viterbi decoding method with the SIMD processor. CONSTITUTION: A parallel arithmetic unit(150) calculates a path value of each source node included in a current column. The parallel arithmetic unit determines each source node included in a previous column and input data corresponding to a path selected by using the path value. A data arrangement unit(170) arranges a input data sequence of each node included in the current column. The parallel arithmetic unit merges the input data of the previous column with the arranged input data of the current column according to a register processing unit. [Reference numerals] (110) Command storage unit; (120) Control unit; (130) Scalar operation unit; (140) Scalar register unit; (150) Parallel arithmetic unit; (160) Parallel register unit; (170) Data arrangement unit; (180) Data storage unit