| 摘要 |
A cryptographic processing device 100 includes an interruption timing judgment circuit 101. The interruption timing judgment circuit 101 includes an interruption timing judgment register 101a, a transfer state reference unit 101b, and an interruption timing judgment unit 101c. The interruption timing judgment register 101a stores a table 200 used by the interruption timing judgment unit 101c to judge whether to interrupt transfer performed by a DMAC 102. The transfer state reference unit 101b monitors how many bytes among blocks read from a memory 14 the DMAC 102 has input into a cryptographic computing circuit 103. The interruption timing judgment unit 101c judges whether to switch a transfer target during transfer of image data by the DMAC 102, based on the table 200 stored in the interruption timing judgment register 101a and a result of the monitoring by the transfer state reference unit 101b (i.e. the number of transferred bytes). |
