发明名称 Resistance semiconductor memory device having a bit line supplied with a compensating current based on a leak current detected during a forming operation
摘要 A semiconductor memory device includes a memory cell array, a first control circuit, and a second control circuit. The first control circuit is configured to apply a first voltage to a selected first line. The second control circuit is configured to apply a second voltage having a voltage value higher than that of the first voltage to a selected second line. The first control circuit includes a detecting circuit. The detecting circuit is configured to detect a leak current to flow from the second line to the first line through a memory cell during a forming operation for bringing the memory cell into a state that allows the memory cell to shift between a high resistance state and a low resistance state. The second control circuit includes a current supply circuit, and a compensating circuit. The current supply circuit is configured to supply a constant current to the second line during the forming operation. The compensating circuit is configured to supply a compensating current having the same current value as that of the leak current to the second line during the forming operation based on the leak current detected by the detecting circuit.
申请公布号 US8331177(B2) 申请公布日期 2012.12.11
申请号 US201113051110 申请日期 2011.03.18
申请人 SASAKI TAKAHIKO;KABUSHIKI KAISHA TOSHIBA 发明人 SASAKI TAKAHIKO
分类号 G11C29/00 主分类号 G11C29/00
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