发明名称 |
Adaptive write bit line and word line adjusting mechanism for memory |
摘要 |
A memory includes a capacitor coupled to a write bit line or a word line. An initializer is configured to initialize a voltage level at a first node between the capacitor and the write bit line or a word line. An initial level adjuster is configured to adjust a voltage level of a second node at one terminal of the capacitor. A pulse generator configured to supply a pulse to the initial level adjuster to control the initial level adjuster. A boost signal is configured to be supplied to a third node on the other terminal of the capacitor opposite the first node to boost a voltage level of the write bit line lower than ground or to boost a voltage level of the word line higher than a power supply voltage. |
申请公布号 |
US8331132(B2) |
申请公布日期 |
2012.12.11 |
申请号 |
US20100849570 |
申请日期 |
2010.08.03 |
申请人 |
CHENG HANK;KUO MING-ZHANG;CHOU CHUNG-CHENG;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHENG HANK;KUO MING-ZHANG;CHOU CHUNG-CHENG |
分类号 |
G11C11/24;G11C7/00;G11C8/00 |
主分类号 |
G11C11/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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