| 摘要 |
Apparatuses and methods for disabling well bias are disclosed. In one embodiment, an apparatus includes a complimentary metal oxide semiconductor (CMOS) switch having a gate, a drain, a source, and a well. The source and drain are formed in the well. The gate is formed adjacent the well between the source and drain, and the source is configured to receive a bias voltage from a power amplifier. The apparatus further includes a well bias control block for biasing the well voltage of the first switch and a disable circuit for disabling the well bias control block so as to prevent the well bias control block from biasing the well. The well bias control block can bias the well voltage of the first switch to at least two voltage levels.
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